The present application claims the benefit of Korean Patent Application No. 2001-23404 filed Apr. 30, 2001, which is herein fully incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a static random access memory (SRAM) cell and a method of fabricating the SRAM cell, which can efficiently contact a gate and a junction region, and which can simultaneously form an LDD region and the junction region according to a single ion implantation process.
2. Description of the Background Art
As a semiconductor device, a conventional SRAM cell will now be explained in brief with reference to FIG. 1 showing an equivalent circuit indicating a memory cell thereof.
In general, the SRAM cell uses a p-type MOS as a load, and consists of six transistors.
In more detail, in the SRAM cell, a pair of access transistors Q3, Q4 (n-type MOS transistors), a pair of driving transistors Q1, Q2 (n-type MOS transistors), and a pair of load transistors Q5, Q6 (p-type MOS transistors) are connected one another to compose a flip-flop circuit.
Here, source regions 110b, 111b of the load transistors Q5, Q6 are connected to a power supply source Vcc, source regions of the driving transistors Q1, Q2 are connected to a ground voltage GND, and the access transistors Q3, Q4 are connected to storage nodes, respectively.
In addition, a bit line 107 is connected to one of source/drain regions of the access transistor Q3, a bit line 108 is connected to one of source/drain regions of the access transistor Q4, and gate electrodes G3, G4 of the access transistors Q3, Q4 are connected to a word line 109.
On the other hand, a drain region 111a of the load transistor Q6 and a gate electrode G5 of the load transistor Q5 are connected to each other through a contact (not shown).
In the above-described SRAM cell, however, it is difficult to form a contact to connect the p-type gate electrode G5 of the load transistor Q5 consisting of the p-type MOS transistor to the drain region 111a of the load transistor Q6 at a region indicated by a dotted circle A in FIG. 1. That is, an oxide film, which is formed on the gate electrode using an oxidation process prior to an application of an ion implantation process to form a junction for minimizing damage of active regions of the semiconductor substrate during the ion implantation process, is not completely removed. Thus, the top surface of the gate electrode is not fully exposed. Accordingly, the gate electrode G5 and the drain region 111a are not successfully connected to each other.
The conventional method for fabricating the SRAM cell will now be described in detail with reference to FIGS. 2 to 5.
FIGS. 2 to 5 are cross-sectional diagrams illustrating sequential steps of the conventional method for fabricating the SRAM cell.
As illustrated in FIG. 2, an undoped polysilicon layer 3 is formed on a semiconductor substrate 1 so as to form a p-type gate. B11 is firstly ion-implanted to the undoped polysilicon layer 3, and then As75 is ion-implanted thereto. Here, As75 is implanted to reduce contact resistance. As shown in FIG. 1, the p-type gate G5, the n-type gate G1, the p-type gate G6 and the n-type gate G2 are connected through one polysilicon to form a PN junction. In the case that a current flows in an NP direction, the PN junction serves as a resistor for controlling a flow of the current.
Accordingly, when the current flows in the NP direction, an ion-implanted region is operated as a path, and the ion-implantation region is formed by ion-implanting As75 to the undoped polysilicon layer 3.
Referring to FIG. 3, although not illustrated, a photoresist film pattern (not shown) exposing a gate formation region is formed on the undoped polysilicon layer 3. The polysilicon layer 3 is selectively patterned by using the photoresist film pattern as a mask, thereby forming a PMOS gate electrode 3a. 
In an ion implantation process for forming a highly doped region and a lightly doped drain (LDD) region, an oxide film 5 is formed on the undoped polysilicon layer 3 according to an oxidation process in order to minimize damage of the active regions of the semiconductor substrate. Here, the oxide film 5 is unevenly grown at a thickness of 400 to 500 xc3x85 which is three or four times as thick as the thickness of an oxide film grown by using a general polysilicon oxidation process.
Thereafter, a low density impurity is ion-implanted to the exposed regions of the semiconductor substrate 1 by using the oxide film 5 and the gate electrode 3a as a mask, to form an LDD region 7 in the semiconductor substrate 1.
As depicted in FIG. 4, an insulating film material layer is then deposited over the resultant structure, and selectively removed according to an anisotropic etching process, thereby forming spacers 9 at the side portions of the oxide film 5 and the gate electrode 3a. 
Thereafter, a high density impurity is ion-implanted to the exposed regions of the semiconductor substrate 1 by using the upper surface of the oxide film 5 and the spacers 9 as a mask, to form HDD regions 11 which will be employed as a source and drain.
As shown in FIG. 5, an interlayer insulating film 13 is deposited over the resultant structure. A photoresist film (not shown) is coated on the interlayer insulating film 13 to expose the HDD regions 11. The photoresist film is then selectively removed according to exposure and development processes of a photolithography process, thereby forming a photoresist film pattern (not shown).
The interlayer insulating film 13 and the oxide film 5 are selectively removed by employing the photoresist film pattern as a mask, to form a contact hole 15 exposing the HDD region 11. In the contact hole formation process, the oxide film 5 is not completely removed, and thus the top surface of the gate electrode 3a is not exposed.
Because of As75 doped at the interface of the ion-implanted polysilicon layer to reduce contact resistance, polysilicon at the interface is oxidized in the oxidation process at a thickness of 400 to 500 xc3x85 which is three or four times as thick as an oxidized layer provided by using the general oxidation process.
Therefore, in the process for connecting the gate electrode and the HDD region which is an active region, a thick portion of the oxide film remains as indicated by a dotted circle C of FIG. 5, and thus the upper surface of the gate 3a electrode is not fully exposed. As a result, the HDD region 11 and the gate electrode 3a are not connected electrically via a material to be formed in the contact hole 15.
In the oxidation process of the polysilicon gate electrode, the upper portion of the side wall 5a of the gate electrode 3a is more oxidized than the lower portion thereof, as indicated by a dotted circle B of FIG. 3. This produces a vertical polysilicon gate having a trapezoidal shape.
Accordingly, resistance of the gate operated as a contact portion of the NMOS gate and the PMOS gate is increased, which reduces the operation speed of the device.
Therefore, it is an object of the present invention to provide a static random access memory (SRAM) cell and a fabrication method thereof which can improve an operation speed of a device by preventing a polysilicon gate from being excessively oxidized.
Another object of the present invention is to provide an SRAM cell and a method for fabricating the SRAM cell which can simplify the entire fabrication process by forming an HDD region and an LDD region according to one ion implantation process.
Still another object of the present invention is to provide an SRAM cell and a method for fabricating the SRAM cell which can improve a process yield by reducing a contact defect between a polysilicon gate and an active region.
In order to achieve the above-described objects of the present invention, there is provided a method for fabricating a static random access memory (SRAM) cell, including the steps of providing a semiconductor substrate; forming a doped polysilicon layer on the semiconductor substrate; forming an undoped polysilicon layer on the doped polysilicon layer; forming a gate by patterning the undoped polysilicon layer and the doped polysilicon layer; forming an oxidation barrier film over the resultant structure including the gate; forming a sacrificial spacer at the side portions of the oxidation barrier film; removing the exposed portion of the oxidation barrier film and the sacrificial spacer; oxidizing the resultant structure according to an oxidation process; forming a lightly-doped drain region and a highly-doped drain region, by ion-implanting a high density impurity to the semiconductor substrate below both side portions of the oxidation barrier film; forming an interlayer insulating film on the exposed surface of the resultant structure; exposing the top surface of the gate and the highly-doped drain region by selectively patterning the interlayer insulating film and the undoped polysilicon layer; and connecting the gate and the highly-doped drain region by forming a conductive material over the resultant structure.
In another aspect of the present invention, a method for fabricating an SRAM cell includes the steps of: providing a semiconductor substrate; forming a polysilicon layer on the semiconductor substrate; doping the polysilicon layer, by sequentially ion-implanting a first conductive type impurity and a second conductive type impurity thereto; forming an undoped polysilicon layer on the doped polysilicon layer; forming a gate by patterning the undoped polysilicon layer and the doped polysilicon layer; forming a nitride film over the resultant structure including the gate; forming a sacrificial spacer at the side portions of the nitride film; removing the exposed portion of the nitride film; removing the sacrificial spacer; oxidizing the resultant structure according to an oxidation process; forming a lightly-doped drain region and a highly-doped drain region at the same time by ion-implanting a high density impurity to the semiconductor substrate below both side portions of the nitride film; forming an interlayer insulating film on the exposed surface of the resultant structure; exposing the top surface of the gate and the highly-doped drain region by selectively patterning the interlayer insulating film, the oxide film and the undoped polysilicon layer; and connecting the gate and the highly-doped drain region by forming a conductive material over the resultant structure.
In still another aspect of the present invention, a method for fabricating an SRAM cell includes the steps of: providing a semiconductor substrate; forming a polysilicon layer on the semiconductor substrate; doping an undoped polysilicon layer by sequentially ion-implanting a p-type impurity and an n-type impurity to the polysilicon layer; forming an undoped polysilicon layer on the doped polysilicon layer; forming a gate by patterning the undoped polysilicon layer and the doped polysilicon layer; forming a nitride film over the resultant structure including the gate; forming a photoresist spacer at the side portions of the nitride film; removing the exposed portion of the nitride film; removing the photoresist spacer; oxidizing the resultant structure according to an oxidation process; forming a lightly-doped drain region and a highly-doped drain region at the same time by ion-implanting a high density impurity to the semiconductor substrate below both side portions of the nitride film; forming an interlayer insulating film on the exposed surface of the resultant structure; exposing the top surface of the gate and the highly-doped drain region by selectively patterning the interlayer insulating film and the undoped polysilicon layer; and connecting the gate and the highly-doped drain region by forming a conductive material over the resultant structure.